Topic: Carbon Nanotube Electronics - Extending Moore’s Law to the End and Beyond the Roadmap
Speaker: Prof. Lianmao, Peng, Peking University
Time: 3:00 p.m., November 7, 2014
Venue: Conference Room on the 1st Floor, Building B5, SCUT South Campus
Sponsor: School of Materials Science and Engineering
Abstract:
Among the candidate channel materials for the next generation electronic devices, semiconducting carbon nanotube (CNT) is unique in that it has no dangling bonds but has perfect Ohmic contacts to both the conduction and valence bands of the CNT. This is extremely important, since it provides the required chemical and mechanical stability of the devices, and renders both n-type and p-type FETs with performance close to ballistic limit available for CNT CMOS. CNT also has high carrier mobility and high saturation velocities, allowing high performance in long channel device where the transport is dominated by diffusive transport, and in short channel device where the device speed is determined by the saturation or Fermi velocity. In addition, a semiconducting CNT has a symmetric band structure near the Fermi level that gives identical effective mass for both electron and hole, leading to symmetric CMOS with potentially very low power consumption and compacted circuit layout. The atomic thickness of the CNT conduction channel is also extremely important in that it allows easier control of the channel current, making the scaling of the CNT technology possible down to 5nm transistor technology.
High performance CNT CMOS devices can be readily fabricated by a doping-free process using symmetric pairs of n-type (Sc or Y) and p-type (Pd) contacts, with demonstrated performance that compares favorably to the state of the art Si MOS FETs down to the very end of the roadmap. The feasibility of this doping free CMOS technology has been demonstrated by fabricating CMOS circuits, including a full adder and BUS circuits, on a SiO2/Si substrate, demonstrating perfect symmetric device characteristics for the n-type and p-type CNT FETs based on the same single walled CNT. This CNT based CMOS technology only requires the patterning of arrays of parallel semiconducting CNTs with moderately narrow diameter range, e.g. 1.5-2.5nm, instead of the more stringent chirality control on the CNT. This may lead to the integration of CNT based CMOS devices or entire carbon based circuit with increasing complexity and possibly find its way into logic and optoelectronic circuits. Precise control on the threshold voltage of the CNT FET is also possible by using gate metal with suitable work function. This threshold voltage control allows zero threshold voltage CMOS devices be fabricated, and highly efficient circuits be built with pass-transistor-logic (PTL) which is more efficient than CMOS and uses much less numbers of transistors for achieving the same logic function. The doping-free approach and ballistic transport of CNT also allow extremely low power supply be used in CNT circuits, the demonstrated 0.4V is significantly lower than the projected 0.56V for Si circuits around 2026, leading to the possibility of using CNT to extend the MOS FET toward the end of the road map.